1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a plurality of memory blocks and, more particularly, it relates to a semiconductor integrated circuit requiring a distinct memory access to each of a plurality of memory blocks.
2. Description of the Related Art
FIG. 1 illustrates a block diagram of the data storage section of a conventional integrated circuit having a memory cell array comprising a plurality of memory blocks. In FIG. 1, a first memory block 10 comprises an array of dual port memory cells 7 that can be independently accessed through either of its two ports, whereas a second memory block 15 comprises an array of single port memory cells 13. A set of word lines 5 of the dual line system of said first memory block 10 are drawn side by side into the second memory block 15. A pair of address buffer circuits 1 and 2 are disposed to receive respective address signals A and B entered through a plurality of (two in this example) external interfaces. Address decoders 3 and 4 are arranged for the respective address buffer circuits 1 and 2. A pair of sense amplifiers 11 and 12 are arranged for the respective dual ports of said first memory block 10. Another sense amplifier 16 is arranged for the second memory block 15. Reference numeral 6 in FIG. 1 denotes the other set of word lines of said first memory block 10 and numerals 8 and 9 respectively denote two different sets of bit lines of said first memory block 10, while reference numeral 14 denotes a set of bit lines of said second memory block 15.
An integrated circuit having a configuration as described above is used when different memory blocks are accessed through a plurality of external interfaces and the delayed timing with which each of the interfaces accesses an appropriate one of the memory blocks of the integrated circuit is defined by a time division cycle signal.
FIG. 2 illustrate an example of a timing chart for operating a memory circuit as shown in FIG. 1. Each of a pair of external interfaces accesses the memory block M1 (i.e., the first memory block 10) by means of an address signal A or B once for each cycle so that the memory block M1 is accessed twice in a cycle. The other memory block M2 (i.e., the second memory block 15), on the other hand, is accessed only by an external interface by means of an address signal A for the full period of each cycle.
It should be noted here that a conventional integrated circuit having a configuration as described above has to have address buffer circuits 1 and 2, decoders 3 and 4, two sets of word lines 5 and 6 as well as two sets of bit lines 8 and 9 and sense amplifiers 11 and 12 for the first memory block in order to accommodate input signals transmitted from a pair of external interfaces, making the overall circuit rather cumbersome if compared with an integrated circuit prepared for a single external interface.
FIG. 3 shows a block diagram of a semiconductor integrated circuit obtained by modifying that of FIG. 1 in an attempt to simplify the circuit configuration, where a memory block comprising an array of single port cells 24 is used for the first memory block 26. Note that the circuit components of FIG. 3 that are identical with those of FIG. 1 are indicated respectively by the same reference numerals. While the first memory block 26 needs to have only a single set of bit lines 8 and a single sense amplifier 11 to handle input signals from a pair of external interfaces, it still requires a decoder 3 for the first memory block 26 to be accessed by two external interfaces, a decoder 21 for the second memory block 15 to be accessed by a single external interface by means of an address signal A, two sets of word lines 22, 23 for output signals from the decoders and a switch 19 for switching address signals to be sent to the decoder 3 of the first memory block 26. In short, at least two decoders 3 and 21 as well as two sets of word lines 22 and 23 need to be there to establish two signal transmission systems.
Thus, up until now, the use of multiple port memories and more than one decoders and word line sets has been indispensable to set up more a plurality of data transmission systems within a conventional semiconductor integrated circuit if any of its memory blocks are to be accessed by more than one external interfaces. Consequently, the overall size of such an integrated circuit and the number of transistors contained in it have been inevitably very large to push up the manufacturing cost, while the data storage capacity that a single chip can provide has been limited. On the other hand, the use of more than one decoders and word line sets in a single integrated circuit can constitute a redundancy of components particularly when it is accessed by a single external interface for many consecutive cycles as only one of the decoders and the corresponding set of word lines are busy then while the other decoder and the other set of word lines remain idle.